View AK4704_1081177.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 1 - general description the AK4704 offers the ideal features for digital set- top-box systems. using akm's multi-bit architecture for its modulator, the AK4704 delivers a wide dynamic range while preserving linearity for improved thd+n performance. the AK4704 integrates a combi nation of scf and ctf filters, removing the need for high cost external filters and increasing performance for systems with excessive clock jitter. the AK4704 also including the audio switches, volumes, video switches, video filters, etc. designed primarily for digital set-top-box systems. the AK4704 is offered in a space saving 48-pin lqfp package. features dac ? sampling rates ranging from 8khz to 50khz ? 64db high attenuation 8x fir digital filter ? 2nd order analog lpf ? on chip buffer with single-ended output ? digital de-emphasis for 32k, 44.1k and 48khz sampling ? i/f format: 24bit msb justified, i 2 s, 18/16bit lsb justified ? master clock: 256fs, 384fs ? high tolerance to clock jitter analog switches for scart audio section ? thd+n: -86db (@2vrms) ? dynamic range: 96db (@2vrms) ? stereo analog volume with ze ro-cross detection circuit (+6db to ?60db & mute) ? six analog inputs two stereo input (tv&vcr scart) one stereo input (changeover to internal dac) ? five analog outputs two stereo outputs (tv, vcr scart) one mono output (modulator) ? pop noise free circuit for power on/off video section ? integrated lpf: -40db@27mhz ? 75ohm driver ? 6db gain for outputs ? adjustable gain ? four cvbs/y inputs (encx2, tv, vcr), three cvbs/y output (rf, tv, vcr) ? three r/c inputs (encx2, vcr) , two r/c output (tv, vcr) ? bi-directional control for vcr-chroma/red ? two g and b inputs (enc, vcr), one g and b outputs (tv) ? y/c mixer for rf output ? vcr input monitor loop-through mode for standby auto-startup mode for power saving scart pin#16(fast blanking), pin#8(slow blanking) control power supply ? 5v+/-5% and 12v+/-5% ? low power dissipation / low power standby mode package ? small 48pin lqfp 2ch 24bit dac with av scart switch AK4704 = target spec =
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 2 - tvoutl monoout tvoutr vcroutl vcroutr +6 to -60db (2db/step) -6db/0db/ +2.44/+4db tvinl tvinr vcrinl vcrinr dac mclk bick lrck sdti bias (mute) volume #0 volume #1 tv1/0 vol mono sck sda register control pdn dvcom pvcom vcr1/0 vd vp vss vmono audio block(dapd=?0?) tvoutl monoout tvoutr vcroutl vcroutr +6 to -60db (2db/step) tvinl tvinr vcrinl vcrinr (nc) dacl dacr (nc) bias (mute) volume #1 tv1/0 vol mono sck sda register control pdn dvcom pvcom vcr1/0 vd vp vss vmono 0db/+6db volume #2 audio block(dapd=?1?)
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 3 - enc c tvrc enc g/cvbs vcr g tvg enc b vcr b tvb enc y tvvout rfv 6db 6db 6db 6db 0, 1, 2, 3db enc r/c vcrvout vcrc 6db 6db vcr cvbs/ y tv cvbs vcr r/c enc cvbs/y encc encg vcrg encb vcrb ency encrc vcrvin tvvin vcrrc encv ( typical connection ) rf mod tv scart vcr scart ( typical connection ) vvd2 vvss vvd1 6db monitor filt video block monitor vcr fb tvfb 6db 0v 2v tvsb vcrsb 0/ 6/ 12v 0/ 6/ 12v vcrfb ( typical connection ) tv scart vcr scart ( typical connection ) int video blanking block
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 4 - ? ordering guide AK4704 -10 +70 c 48pin lqfp (0.5mm pitch) ? pin layout vcrc tvfb 1 vvd1 48 2 vvss 3 tvvout 4 vvd2 5 tvrc 6 7 tvg 8 tvb 9 encb 10 encg 11 vcrvout 47 rfv 46 pdn 45 sda 44 scl 43 lrck 42 sdti 41 bick 40 mclk 39 vd 38 encv 13 ency 14 tvvin 15 vcrvin 16 vcrfb 17 vcrrc 18 vcrg 19 vcrb 20 int 21 vcrsb 22 tvsb 23 35 34 33 32 31 30 29 28 27 26 25 dvcom vp vcroutl vcroutr filt tvinl monoout tvoutl tvoutr tvinr vcrinl top view encrc 12 vcrinr 24 36 pvcom vss 37 encc ? main difference between ak4702 and AK4704 items ak4702 AK4704 audio audio bits 18bit 24bit digital filter attenuation level 54db 64db +4db gain at dac volume#0 (total: +10db max) - x dac power-down/analog input mode - x volume#1 output for vcroutl/r switch matrix - x mono mixing for vcroutl/r - x mono input x - video video filter - x 150ohm video driver for modulator - x y/c mixer for modulator - x vcr video input monitor - x vcr slow blanking monitor in output mode. enabled disabled tv/vcr cvbs input detection & power save mode - x i 2 c speed (max) 100khz 400khz others mask bits for int function (09h) - x -: not available. x: available
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 5 - pin/function no. pin name i/o function 1 vcrc o chrominance output pin for vcr 2 vvss - video ground pin. 0v. 3 tvvout o composite/luminance output pin for tv 4 vvd2 - video power supply pin #2. 5v. normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 5 tvrc o red/chrominance output pin for tv 6 tvg o green output pin for tv 7 tvb o blue output pin for tv 8 vvd1 - video power supply pin #1. 5v. normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 9 encb i blue input pin for encoder 10 encg i green input pin for encoder 11 encrc i red/chrominance input pin1 for encoder 12 encc i chrominance input pin2 for encoder 13 encv i composite/luminance input pin1 for encoder 14 ency i composite/luminance input pin2 for encoder 15 tvvin i composite/luminance input pin for tv 16 vcrvin i composite/luminance input pin for vcr 17 vcrfb i fast blanking input pin for vcr 18 vcrrc i red/chrominance input pin for vcr 19 vcrg i green input pin for vcr 20 vcrb i blue input pin for vcr 21 int o interrupt pin for video blanking 22 vcrsb i/o slow blanking input/output pin for vcr 23 tvsb o slow blanking output pin for tv 24 vcrinr i rch vcr audio input pin 25 vcrinl i lch vcr audio input pin 26 tvinr i rch tv audio input pin 27 tvinl i lch tv audio input pin 28 filt o filter pin normally connected to vvss with a 0.1 f ceramic capacitor. 29 vcroutr o rch analog output pin1 30 vcroutl o lch analog output pin1 31 tvoutr o rch analog output pin2 32 tvoutl o lch analog output pin2 33 monoout o mono analog output pin 34 vp - power supply pin. 12v. normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 35 dvcom o dac common voltage pin normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 36 pvcom o audio common voltage pin normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. the caps affect the settling time of audio bias level.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 6 - pin/function (continued) 37 vss - ground pin. 0v. 38 vd - dac power supply pin. 5v. normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 39 mclk (nc) i - master clock input pin at dapd=?0?. nc (no connection) pin at dapd=?1?. 40 bick dacr i - audio serial data clock pin at dapd=?0?. rch analog audio input pin at dapd=?1?. 41 sdti (nc) i i audio serial data input pin at dapd=?0?. nc (no connection) pin at dapd=?1?. 42 lrck dacl i i l/r clock pin at dapd=?0?. lch analog audio input pin at dapd=?1?. 43 scl i control data clock pin 44 sda i/o control data pin 45 pdn i power-down mode pin when at ?l?, the AK4704 is in the power-down mode and is held in reset. the AK4704 should always be reset upon power-up. 46 rfv o composite output pin for rf modulator 47 vcrvout o composite/luminance output pin for vcr 48 tvfb o fast blanking output pin for tv note: all input pins should not be left floating.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 7 - internal equivalent circuits pin no. pin name type equivalent circuit description 39 40 41 42 43 45 mclk bick sdti lrck scl pdn digital in (dapd="0") analog in (dapd="1") vd 200 vss (60k) the 60kohm is attached only for bick and lrck. 44 sda digital i/o vd vss 200 i2c bus voltage must not exceed vd. 21 int digital out v ss vp normally connected to vd(5v) through 10kohm resistor externally. 46 47 48 1 3 5 6 7 rfv vcrout tvfb vcrc tvvout tvrc tvg tvb video out vvd1 vvss vvd2 vvss 28 filt filter out vp vss vss 200 1k vd 68k normally connected to vvss (0v) through 0.1f capacitor externally.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 8 - pin no. pin name type equivalent circuit description 9 10 11 12 13 14 15 16 17 18 19 20 encb encg encrc encc encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb video in vvd1 200 vvss 22 23 vcrsb tvsb video sb vp vss vp vss vss 200 (120k) the 120kohm is not attached for tvsb. 24 25 26 27 vcrinr vcrinl tvinr tvinl audio in vp 200 vss 29 30 31 32 33 vcroutr vcroutl tvoutr tvoutl monoou t audio out vp vss vp vss 100 35 36 dvcom pvcom vcom out vd vss vd vss 100 vd vss
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 9 - absolute maximum ratings (vss=vvss=0v;note: 1) parameter symbol min max units power supply vd vvd1 vvd2 vp |vss-vvss| (note: 2) -0.3 -0.3 -0.3 -0.3 - 6.0 6.0 6.0 14 0.3 v v v v v input current (any pins except for supplies) iin - 10 ma input voltage vind -0.3 vd+0.3 v video input voltage vinv -0.3 vvd1+0.3 v audio input voltage (except dacl/r pins) vina -0.3 vp+0.3 v audio input voltage (dacl/r pins) vina -0.3 vd+0.3 v ambient operating temperature ta -10 70 c storage temperature tstg -65 150 c note: 1. all voltages with respect to ground. note: 2. vss and vvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss=vvss=0v; note: 1) parameter symbol min typ max units power supply vd vvd1=vvd2 vp 4.75 4.75 11.4 5.0 5.0 12 5.25 5.25 12.6 v v v note: 3. analog output voltage scales with the voltage of vd. aout (typ@0db) = 2vrms vd/5. *akm assumes no responsibility for the usage beyond the conditions in this datasheet. electrical characteristics (ta = 25 c; vp=12v, vd = 5v; vvd1=vvd2 = 5v; fs = 48khz; bick = 64fs) power supplies power supply current normal operation (pdn = ?h?; note: 4) vd vvd1+vvd2 vp power-down mode (pdn = ?l?; note: 5) vd vvd1+vvd2 vp tbd tbd tbd 10 10 10 tbd tbd tbd 100 100 100 ma ma ma a a a note: 4. stby bit ="l", all video outputs active. no signal, no load for a/v switches. fs=48khz ?0?data input for dac. note: 5. all digital inputs including clock pins (mclk, bick and lrck) are held at vd or vss.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 10 - digital characteristics (ta = 25 c; vd = 4.75 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.0 - - - - 0.8 v v low-level output voltage (sda pin: iout= 3ma, int pin: iout= 1ma) vol - - 0.4 v input leakage current iin - - 100 a analog characteristics (audio) (ta = 25 c; vp=12v, vd = 5v; vvd1=vvd2 = 5v; fs = 48khz; bick = 64fs; signal frequency = 1khz; 24bit input data; measurement frequency = 20hz 20khz; r l 4.5k ? ; volume #0=volume #1=0db, 0db=2vrms output; unless otherwise specified) parameter min typ max units dac resolution 24 bit analog input: (tvinl/tvinr/vcrinl/vcrinr pins) analog input characteristics input voltage 2 vrms input resistance 100 150 - k ? analog input: (dacl/dacr pin) analog input characteristics input voltage 1 vrms input resistance tbd tbd - k ? stereo/mono output: (tvoutl/tvoutr/vcroutl/vcroutr/monoout pins; note: 6) analog output characteristics volume#0 gain (dvol1-0 = ?00?) (dvol1-0 = ?01?) (dvol1-0 = ?10?) (dvol1-0 = ?11?. note: 7) 0 -6 +2.44 +4 db db db db volume#1 step width (+6db to ?12db) (-12db to ?40db) (-40db to ?60db) 1.6 0.5 0.1 2 2 2 2.4 3.5 3.9 db db db thd+n (at 2vrms output. note: 8) ( at 3vrms output. note: 8, note: 9) -86 -60 -80 - db db dynamic range (-60db output, a-weighted. note: 8) 92 96 db s/n (a-weighted. note: 8) 92 96 db interchannel isolation (note: 8, note: 10) 80 90 db interchannel gain mismatch (note: 8, note: 10) - 0.3 - db gain drift - 200 - ppm/ c load resistance (ac-lord; note: 11) tvoutl/r, vcroutl/r, monoout 4.5 k ? output voltage (note: 11, note: 12) 1.85 2 2.15 vrms power supply rejection (psr. note: 13) - 50 db note: 6. measured by audio precision system two cascade. note: 7. output clips over ?2.5dbfs digital input. note: 8. dac to tvout note: 9. except vcroutl/vcroutl pins. note: 10. between tvoutl and tvoutr with digital inputs 1khz/0dbfs. note: 11. thd+n : -80db(min. at 2vrns), -60db(typ. at 3vrms). note: 12. full-scale output voltage by dac (0dbfs). output voltage of dac scales with the voltage of vd, stereo output (typ@0dbfs) = 2vrms vd/5 when volume#0=volume#1=0db. do not output signals over 3vrms. note: 13. the psr is applied to vd with 1khz, 100mv.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 11 - filter characteristics (ta = 25 c; vp=11.4 12.6v, vd = 4.75 5.25v, vvd1=vvd2 = 4.75 5.25v; fs = 48khz; dem0 = ?1?, dem1 = ?0?) parameter symbol min typ max units digital filter passband 0.05db (note: 14) -6.0db pb 0 - 24.0 21.77 - khz khz stopband (note: 14) sb 26.23 khz passband ripple pr 0.01 db stopband attenuation sa 64 db group delay (note: 15) gd - 24 - 1/fs digital filter + lpf frequency response 0 20.0khz fr - 0.5 - db note: 14. the passband and stopband frequencies scale with fs (system sampling rate). e.g.) pb=0.4535fs (@ 0.05db), sb=0.546fs. note: 15. the calculating delay time which occurred by digital fi ltering. this time is from setting the 16/18/24bit data of both channels to input register to the output of analog signal.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 12 - analog characteristics (video) (ta = 25 c; vp=12v, vd = 5v; vvd1=vvd2 = 5v; vvol1/0= ?00?, yc=?0? unless specified.) parameter conditions min typ max units sync tip clamp voltage at output pin. 0.7 v chrominance bias voltage at output pin. 2.2 v gain input=0.3vp-p, 100khz 5.5 6 6.5 db vvol1/0= ?00? 5.5 6 6.5 db vvol1/0= ?01? 6.7 7.2 7.7 db vvol1/0= ?10? 7.7 8.2 8.7 db rgb gain input=0.3vp-p, 100khz vvol1/0= ?11? 8.6 9.1 9.6 db interchannel gain mismatch tvrc, tvg, tvb. input=0.3vp-p, 100khz. -0.3 - 0.3 db frequency response input=0.3vp-p, c1=c2=0pf. 100khz to 6mhz. at 12mhz. at 27mhz. -1.0 -3 -40 0.5 -35 db db db group delay distortion at 4.43mhz with respect to 1mhz. 15 ns input impedance chrominance input (internally biased) 40 60 - kohm input signal f=100khz, maximum with distortion < 1.0%, gain=6db. - - 1.5 vpp load resistance (note: 16) 150 - - ohm load capacitance c1 (note: 16) c2 (note: 16) 400 15 pf pf dynamic output signal f=100khz, maximum with distortion < 1.0% - - 3 vpp y/c crosstalk f=4.43mhz, 1vp-p input. among tvvout, tvrc, vcrvout and vcrc outputs. - -50 - db s/n reference level = 0.7vp-p, ccir 567 weighting. bw= 15khz to 5mhz. - 74 - db differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - tbd - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - tbd - degree note: 16. refer the figure 1. video signal output 75 ohm 75 oh m max: 400pf c1 r1 r2 max: 15pf c2 figure 1. load resistance r1+r2 and load capacitance c1/c2.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 13 - switching characteristics (ta = 25 c; vp=11.4 12.6v, vd = 4.75 5.25v, vvd1=vvd2 = 4.75 5.25v; c l = 20pf) parameter symbol min typ max units master clock frequency 256fs: duty cycle 384fs: duty cycle fclk dclk fclk dclk 2.048 40 3.072 40 12.8 60 19.2 60 mhz % mhz % lrck frequency duty cycle fs duty 8 45 50 55 khz % audio interface timing bick period bick pulse width low pulse width high bick ? ? to lrck edge (note: 17) lrck edge to bick ? ? (note: 17) sdti hold time sdti setup time tbck tbckl tbckh tblr tlrb tsdh tsds 312.5 100 100 50 50 50 50 ns ns ns ns ns ns ns control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note: 18) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 khz s s s s s s s s s s ns reset timing pdn pulse width (note: 19) tpd 150 ns note: 17. bick rising edge must not occur at the same time as lrck edge. note: 18. data must be held for sufficient time to bridge the 300 ns transition time of scl. note: 19. the AK4704 should be reset by pdn= ?l? upon power up. note: 20. i 2 c is a registered trademark of philips semiconductors. purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the system conform to the i 2 c specifications defined by philips.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 14 - ? timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr serial interface timing
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 15 - tpd vil pdn power-down timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 16 - operation overview 1. system reset and power-down options the AK4704 should be reset once by bringing pdn pin = ?l? upon power-up. the AK4704 has several operation modes. the pdn pin, auto bit, dapd bit, mute bit and stby bit control operation modes as shown in table 1 and table 2. mode pdn pin auto bit stby bit mute bit dapd bit mode 0 ?l? * * * * full power-down 1 ?h? 1 * * * auto startup mode (power-on default) 2 ?h? 0 1 1 * standby & mute 3 ?h? 0 1 0 * standby 4 ?h? 0 0 1 1 mute (dac power down) 5 ?h? 0 0 1 0 mute (dac operation) 6 ?h? 0 0 0 1 normal operation (dac power down & analog input) 7 ?h? 0 0 0 0 normal operation (dac operation) *: don?t care table 1. operation mode settings mode register control mclk, bick, lrck audio bias level video output tvfb, tvsb vcrsb 0 full power-down not available not needed power down hi-z hi-z pull- down (**) 1 auto startup mode (power-on default) no video input available video input (***) active active (****) active active 2 standby & mute power down hi-z/ active 3 standby active 4 mute (dac power down) power down 5 mute (dac operation) needed 6 normal operation (dac power down & analog input) not needed active (*) 7 normal operation (dac operation) needed (*): tvoutl/r are muted by vmute bit in the default state. (**): internally pulled down by 120kohm(typ) resister. (***): video input to tvvin or vcrvin. (****): vcrc outputs 0v for termination. table 2. status of each operation modes
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 17 - ? full power-down mode the AK4704 should be reset once by bringing pdn= ?l? upon power-up. pdn pin: power down pin ?h?: normal operation ?l?: device power down. ? auto startup mode after when the pdn pin is set to ?h?, the AK4704 is in the auto startup mode. in this mode, all blocks except for the video detection circuit are powered down. once the video detection circuit detects video signal from tvvin pin or vcrvin pin, the AK4704 goes to the stand-by mode automatically and sends ?h? pulse via int pin. to exit the auto startup mode, set the auto bit to ?0?. auto bit (00h d3): auto startup bit ?1?: auto startup enable (default). ?0?: auto startup disable (manual startup). ? dac power-down mode the internal dac block can be powered-down and switched to 1vrms analog input mode. when dapd bit =?1?, the zero-cross detection and offset calibration does not work. dapd bit (00h d2): dac power-down bit. ?1?: dac power-down. analog-input mode. #39 pin: mclk -> (nc) #40 pin: bick -> dacr. rch analog input. #41 pin: sdti -> (nc) #42 pin: lrck -> dacl. lch analog input. ?0?: dac operation. (default) ? standby mode when the auto bit = mute bit = ?0? and the stby bit = ?1?, the AK4704 is forced into tv-vcr loop through mode. in this mode, the sources of tvoutl/r and monoout pins are fixed to vcrinl/r pins; the sources of vcroutl/r are fixed to tvinl/r pins respectively. the gain of volume#1 is fixed to 0db. all register values themselves are not changed by stby bit = ?1?. stby bit (00h d0): standby bit. ?1?: standby mode. (default) ?0?: normal operation. ? mute mode (bias- off mode. 00h: d1) when the mute bit = ?1?, the bias voltage on the audio output goes to gnd level. bringing mute bit to ?0? changes this bias voltage smoothly from gnd to vp/2 by 2sec(typ.). this removes the huge click noise related the sudden change of bias voltage at power-on. the change of mute bit from ?1? to ?0? also makes smooth transient from vp/2 to gnd by 2sec(typ). this removes the huge click noise related the sudden change of bias voltage at power-off. mute bit: bias-off bit. ?1?: set the audio bias to gnd. (default) ?0?: normal operation ? normal operation mode to use the dac or change analog switches, set the auto bit, dapd bit, mute bit and stby bit to ?0?. the dac is in power-down mode until mclk and lrck are input. the AK4704 is in power-down mode until mclk and lrck are input. the figure 2 shows an example of the system timing at the power-down and power-up by pdn pin.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 18 - ? typical operation sequence (auto setup mode) the figure 2 shows an example of the system timing at auto setup mode. pdn pin a udio out (dc) don?t care clock, data in tvvout, vcrvout active (loop-through) tvvin signal in no signal don?t care signal in no signal don?t care vcrvin signal in no signal don?t care don?t care active (loop-through) hi-z hi-z active (loop-through) (gnd) active (loop-through) no signal no signal hi-z low power mode low power mode low power mode figure 2. typical operating sequence (auto setup mode) ? typical operation sequence (except auto setup mode) the figure 3 shows an example of the system timing at auto setup mode. pdn p in gd d/a out (internal) (1) tv out ?1? (default) stby bit ?0? ?1? don?t care (2) clock in normal operation don?t care (2) don?t care data in don?t care ?0? gd (1) ?0? dac tv-source select vcr in vcr in ?1? (default) mute bit ?0? ?stand-by? vcr in (3) vcr in fixed to vcr in(loop-through) ?1? ?0? ?stand-by? ?mute? audio data ?1? (default) offset calibration (4) ?1? (default) a uto bit ?0? notes: (1) the analog output corresponding to the digital input has a group delay, gd. (2) the external clocks (mclk, bick and lrck) can be stopped in standby mode. (3) mute the analog outputs externally if click noise(3) adversely affects the system. (4) in case of the cal bit = ?1?, the offset calibration is always executed when the source of tvoutl/r pins are switched to dac after the stby bit is changed to ?0?. to disable this function, set the cal bit = ?0?. figure 3. typical operating sequence (except auto setup mode)
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 19 - 2. audio block ? system clock the external clocks required to operate the dac section of AK4704 are mclk, lrck and bick. the master clock (mclk) corresponds to 256fs or 384fs. mclk frequency is automatically detected, and the internal master clock becomes 256fs. the mclk should be synchronized with lrck but the phase is not critical. table 3 illustrates corresponding clock frequencies. all external clocks (mclk, bick and lrck) should always be present whenever the dac section of AK4704 is in the normal operating mode (stby bit = ?0? and dapd bit = ?0?). if these clocks are not provided, the AK4704 may draw excess current because the device utilizes dynamically refreshed logic internally. the dac section of AK4704 should be reset by stby bit = ?0? after threse clocks are provided. if the external clocks are not present, place the AK4704 in power-down mode (stby bit = ?1?). after exiting reset at power-up etc., the AK4704 remains in power-down mode until mclk and lrck are input. lrck mclk bick fs 256fs 384fs 64fs 32.0khz 8.1920mhz 12.2880mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 3.0720mhz table 3. system clock example ? audio serial interface format (00h: d5-d4) data is shifted in via the sdti pin using bick and lrck inputs. the dif0 and dif1 bits can select four formats in serial mode as shown in table 4. in all modes, the serial data is msb-first, 2?s compliment format and is latched on the rising edge of bick. mode 2 can also be used for 16 msb justified formats by zeroing the unused two lsbs. mode dif1 dif0 sdti format bick figure 0 0 0 16bit lsb justified 32fs figure 4 1 0 1 18bit lsb justified 36fs figure 4 2 1 0 24bit msb justified 48fs figure 5 3 1 1 24bit i 2 s compatible 48fs or 32fs figure 6 default table 4. audio data formats sdti lrck bick 14 0 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb sdti mode 1 17:msb, 0:lsb 15 14 0 15 14 0 don?t care don?t care 17 16 17 16 lch data rch data 15 15 figure 4. mode 0,1 timing
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 20 - lrck bick sdti 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 22 1 0don?t care 23 16 17 figure 5. mode 2 timing lrck bick sdti 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 22 1 0 don?t care 23 17 figure 6. mode 3 timing ? de-emphasis filter (00h: d7-d6) a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is controlled by the dem0 and dem1 bits. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 5. de-emphasis filter control
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 21 - ? volume/switch control the AK4704 has analog volume controls and switch matrix es designed primarily for scart routing. those are controlled via the control register as shown in, table 6, tabl e 8, table 10 and table 11 (please refer to the block diagram in figure 1). (03h: d4-d3) dvol1 dvol0 volume #0 gain output level 0 0 0db 2vrms (with 0dbfs input & volume #1=0db.) 0 1 -6db 1vrms (with 0dbfs input & volume #1=0db.) 1 0 +2.44db 2.65vrms (with 0dbfs input & volume #1=0db.) 1 1 +4db 2vrms (with ?10dbfs input & volume #1=+6db. clips over ?2.5dbfs digital input.) table 6. volume #0 (at dapd bit =?0?. dac mode) (03h: d4-d3) dvol1 dvol0 volume #2 gain output level 0 0 +6db 2vrms (with 1vrms input & volume #1=0db.) 0 1 0db 1vrms (with 1vrms input & volume #1=0db.) 1 0 (reserved) - 1 1 (reserved) - table 7. volume #2 (at dapd bit =?1?. analog input mode.) (02h: d5-d0) l5 l4 l3 l2 l1 l0 gain 1 0 0 0 1 0 +6db 1 0 0 0 0 1 +4db 1 0 0 0 0 0 +2db 0 1 1 1 1 1 0db (default) ? ? ? ? ? ? ? 0 0 0 0 0 1 -60db 0 0 0 0 0 0 mute note: do not exceed 3vrms at analog output. table 8. volume #1 (analog volume) (01h: d1-d0) tv1 tv0 source of tvoutl/r 0 0 dac 0 1 vcrin (default) 1 0 mute 1 1 (reserved) table 9. tvout switch configuration
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 22 - (01h: d2-d0) vol tv1 tv0 source of monoout 0 0 0 dac (l+r)/2 0 0 1 dac (l+r)/2 0 1 0 dac (l+r)/2 bypass the volume #1 0 1 1 (reserved) 1 0 0 dac (l+r)/2 1 0 1 vcrin (l+r)/2 through the volume #1 1 1 0 mute 1 1 1 (reserved) table 10. monoout switch configuration (01h: d5-d4) vcr1 vcr0 source of vcroutl/r 0 0 dac 0 1 tvin (default) 1 0 mute 1 1 output of volume #1 table 11. vcrout switch configuration
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 23 - ? zero-cross detection and offset calibration to minimize the click noise at changing the gain of volume #1, the AK4704 has a zero-cross detection and an offset calibration function. when dapd bit =?1?, the zero-cross detection and offset calibration does not work. 1. zero-cross detection function (03h: d2-d0) when the zero bit = ?1?, the zero-cross detection function is enabled. the gain of volume #1 changes at the first zero-cross point from the acknowledgement of a volume changing command or when the zero-cross is not detected within the time set by ztm1-0 bits (256/fs to 2048/fs). the zero-cross counter is initialized whenever a gain is issued. the zero-cross is detected on l/r channels independently. to disable this function, set the zero bit to ?0?. zero: zero-cross detection enable for volume #1 0 : disable. the volume value changes immediately without zero-cross. 1 : enable (default). the volume value changes at a zero-crossing point or when timeout (ztm1-0 bit setting) occurs. the internal comparator for zero-cross detection has a small offset. therefore, the gain of volume #1 may change due to a zero-cross timeout before the comparator-based zero-cross detection occurs. when the new gain value 1eh(-2db) is written while the gain of both lch and rch are 1fh(0db), if the lch detects the zero-cross prior to rch, only the gain of lch changes to 1eh(- 2db) while rch waits for a zero-cross. after that, if the gain is set to 1dh(-4db) before either a zero-cross or zero-cross timeout, the rch keeps the same value and changes from 1fh to 1dh at next zero-cross or timeout. 1fh lch gain rch gain gain registers zero-cross 1fh 1eh 1dh 1dh 1eh 1fh 1dh wr[gain=1eh] wr[gain=1dh] zero-cross timer initialized timeout; (may have click noise) timer (256/fs to2048/fs) figure 7. zero-cross operation (zero= ?1?) 2. offset calibration function (03h: d5) offset calibration is enabled when the cal bit = ?1?. this function begins when the tvout source is switched to dac after the stby bit is changed to ?0?. it takes 1664/fs to execute the offset calibration cycle. during the offset calibration cycle, the analog outputs are muted. once the offset calibrati on is executed, the calibration memory is held until pdn pin = ?l? or the new calibration is executed. when the switch is changed from dac to vcr during calibration, the calibration is discontinued, and resumed when tvout is switched back to dac. if volume #1 gain is changed during calibration, the change takes place after calibration is complete.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 24 - 3. video block ? video switch control the AK4704 has switches for tv, vcr and rf modulator. each switches can be controlled via registers independently. when auto bit = ?1? or stby bit = ?1?, these switch setting are ignored and set to fixed configuration (loop-through mode). please refer the auto setup mode and standby mode. (04h: d2-d0) mode vtv2-0 bit source of tvvout pin source of tvrc pin source of tvg pin source of tvb pin shutdown 000 (hi-z) (hi-z) (hi-z) (hi-z) encoder cvbs /rgb 001 encv pin encrc pin encg pin encb pin encoder y/c 1 010 encv pin encrc pin hi-z (hi-z) encoder y/c 2 011 ency pin encc pin hi-z (hi-z) vcr (default) 100 vcrvin pin vcrrc pin vcrg pin vcrb pin tv cvbs 101 tvvin pin (hi-z) (hi-z) (hi-z) (reserved) 110 - - - - (reserved) 111 - - - - (please refer notes) table 12. tv video output (04h: d5-d3) mode vvcr2-0 bit source of vcrvout pin source of vcrc pin shutdown 000 (hi-z) (hi-z) encoder cvbs or y/c 1 001 encv pin encrc pin encoder cvbs or y/c 2 010 ency pin encc pin tv cvbs (default) 011 tvvin pin (hi-z) vcr 100 vcrvin pin vcrrc pin (reserved) 101 - - (reserved) 110 - - (reserved) 111 - - (please refer notes) table 13. vcr video output (04h: d7-d6) mode vrf1-0 bit source of rfv pin encoder cvbs1 00 encv pin encoder cvbs2 01 encg pin (note: 22) vcr (default) 10 vcrvin pin shutdown 11 (hi-z) (when yc bit=0. please refer notes) table 14. rf video output note: 21: when input the video signal via encrc pin or vcrrc pin, set clamp1-0 bits respectively. note: 22 when vtv2-0 bit =?001?, tvg bit =?1? and vrf1-0 bit =?01?, rfv pin output is same as tvg pin output (encoder g).
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 25 - ? video output control (05h: d6-d0) each video outputs can be set to hi-z individually via control registers. these setting are ignored when the auto bit = ?1?. when the cio bit = ?1?, the vcrc pin outputs 0v even if the vcrc bit = ?0?. when the cio bit = ?0?, the vcrc pin follows the setting of vcrc bit. please refer the ?red/chroma bi-directional control for vcr scart? tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control tvfb: tvfb output control 0: hi-z (default) 1: active. ? red/chroma bi-directional control for vcr scart (05h: d7, d5) the 4704 supports the bi-directional red/chroma signal on the vcr scart. (AK4704) vcrrc pin vcrc pin vcr scart 75 0.1u (cio bit & vcrc bit) #15 pin figure 8. red/chroma bi-directional control cio vcrc state of vcrc pin 0 0 hi-z (default) 0 1 active 1 0 connected to gnd 1 1 connected to gnd table 15 red/chroma bi-directional control
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 26 - ? rgb video gain control (06h: d1-d0) vvol1-0 bits set the rgb video gain. vvol1 vvol0 gain output level (typ. @input=0.7vpp) 0 0 +6db 1.4vpp (default) 0 1 +7.2db 1.6vpp 1 0 +8.2db 1.8vpp 1 1 +9.1db 2.0vpp table 16. rgb video gain control ? clamp and dc-restore circuit control (06h: d6-d5, d3-d2) each cvbs and y input has the sync tip clamp circuit. the sync tip voltage at each output is 0.7v(typ). this corresponds 0.35v(typ) at the scart connector when matched by 75ohm resisters. the clamp1 and clamp0 bits select the input circuit for encrc pin (encoder red/chroma) and vcrrc pin (vcr red/chroma) respectively. vclp1-0 bits select the source of dc- restore circuit. clamp1 : encoder red/chroma (encrc pin)input clamp control 0 : dc restore clamp active (for red signal. default) 1 : biased (for chroma signal.) clamp0 : vcr r/c (vcrrc pin)input clamp control 0 : dc restore clamp active (for red signal) 1 : biased (for chroma signal. default.) vclp1-0 : dc restore source control vclp1 vclp0 sync source of dc restore 0 0 encv (default) 0 1 ency 1 0 vcrvin 1 1 (reserved) when the auto bit = ?1?, the source is fixed to vcrvin. table 17. dc restore source control ? y/c mixer for rf modulator (06h: d4) when the yc bit = ?1?, the rfv pin outputs y/c mixed signal from tvvout pin and tvrc pin. yc : y/c mixing output control for rfv pin 0 : follow vrf1-0 bits (default) 1 : y/c mixing from tvvout and tvrc.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 27 - 4. blanking control the AK4704 supports fast blanking signals and slow blanking (function switching) signals for tv/vcr scart. ? input/output control for fast/slow blanking fb1-0: tv fast blanking output control (07h: d1-d0) fb1 fb0 tvfb pin output level 0 0 0v (default) 0 1 4v 1 0 same as vcr fb input (4v/0v) 1 1 (reserved) (note: minimum load is 150ohm) table 18. tv fast blanking output sbt1-0: tv slow blanking output control (07h: d3-d2) sbt1 sbt0 tvsb pin output level 0 0 <2v (default) 0 1 5v<, <7v 1 0 (reserved) 1 1 10v< (note: minimum load is 10kohm) table 19. tv slow blanking output sbv1-0: vcr slow blanking output control (07h: d5-d4) sbv1 sbv0 vcrsb pin output level 0 0 <2v (default) 0 1 5v<, <7v 1 0 (reserved) 1 1 10v< (note: minimum load is 10kohm) table 20. vcr slow blanking output sbio1-0: tv/vcr slow blanking i/o control (07h: d7-d6) sbio1 sbio0 vcrsb pin direction tvsb pin direction 0 0 output (controlled by sbv1,0) output (controlled by sbt1,0) (default) 0 1 (reserved) (reserved) 1 0 input (stored in svcr1,0) output (controlled by sbt1,0) 1 1 input (stored in svcr1,0) output (same output as vcr sb) table 21. tv/vcr slow blanking i/o control
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 28 - 5. monitor options and int function ? monitor options (08h: d3-d0) the AK4704 has several monitors for the input dc level of vcr slow blanking, the input dc level of vcr fast blanking and signals input to tvvin or vcrvin pins. svcr1-0 bits , fvcr bit and vmon bit are reflected to these values. svcr1-0: vcr slow blanking status monitor svcr1-0 reflect the voltage at vcrsb pin only when the vcrsb is in the input mode. when the vcrsb is in the output mode, svcr1-0 hold previous value. vcrsb pin input level svcr1 svcr0 < 2v 0 0 4.5 to 7v 0 1 (reserved) 1 0 9.5< 1 1 table 22. vcr slow blanking monitor fvcr: vcr fast blanking input level monitor this bit is enabled when tvfb bit = ?1?. vcrfb pin input level fvcr <0.4v 0 1 v< 1 table 23. vcr fast blanking monitor (typical threshold is 0.7v) vmon : video input monitor 0 : no video signal detected via tvvin pin and vcrvin pin. 1 : detects video signal via tvvin pin or vcrvin pin. ? int function and mask options (09h: d3-d1) changes of the 08h status can be monitored via the int pin. the int pin is the open drain output and goes ?l? for 2usec(typ.) when the status of 08h is changed. this pin should be connected to vd (typ. 5v) through 10kohm resister. mvmon bit, mfvcr bit and msvcr bit control the reflection of the status change of these monitors onto the int pin from report to prevent to masks each monitor mvmon: video input monitor mask. auto mvmon reflection of the change of vmon bit to int pin 0 0 reflect 0 1 not reflect (e.g. masked) 1 0 reflect 1 1 reflect (default) table 24. reflection of vmon change mfvcr: fvcr monitor mask. 0 : change of mfvcr is reflected to int pin. (default) 1 : change of mfvcr is not reflected to int pin. msvcr: svcr1-0 monitor mask. 0 : change of svcr1-0 is reflected to int pin. (default) 1 : change of svcr1-0 is not reflected to int pin.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 29 - 6. control interface i 2 c-bus control mode 1. write operations figure 9 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 15). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit which is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010001?. if the slave address match that of the AK4704, the AK4704 generates the acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 16). a ?1? for r/w bit indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the address for control registers of the AK4704. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 11). the data after the second byte contain control data. the format is msb first, 8bits (figure 12). the AK4704 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 15). the AK4704 can execute multiple one byte write operations in a sequence. after receipt of the third byte, the AK4704 generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 09h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 17) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k figure 9. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 1 r/w figure 10. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 11. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 12. byte structure after the second byte
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 30 - 2. read operations set r/w bit = ?1? for read operations. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cycle after the receipt the first data word. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 09h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the AK4704 supports two basic read operations: current address read and random read. 2-1. current address read the AK4704 contains an internal address counter that maintain s the address of the last word accessed, incremented by one. therefore, if the last access (either a read or writ e) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the AK4704 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4704 discontinues transmission sda s t a r t a c k a c k s slave a ddress a c k data(n+1) p s t o p data(n+x) a c k data(n+2) a c k r/w= ?1? a c k data(n) figure 13. current address read 2-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start condition, slave address(r/w=?0?) and then the register address to read. after the register?s address is acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to ?1?. then the AK4704 generates an acknowledge, 1-byte data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4704 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k sub a ddress(n) s t a r t a c k s slave a ddress r/w= ?1? figure 14. random address read
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 31 - scl sda stop condition start condition s p figure 15. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 16. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 17. bit transfer on the i 2 c-bus
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 32 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control dem1 dem0 dif1 dif0 auto dapd mute stby 01h switch vmute 0 vcr1 vcr0 mono vol tv1 tv0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 03h zerocross 0 vmono cal dvol1 dvol0 zero ztm1 ztm0 04h video switch vrf1 vrf0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 05h video output enable cio tvfb vcrc vcrv tvb tvg tvr tvv 06h video volume/clamp 0 vclp1 vclp0 yc clamp1 clamp0 vvol1 vvol0 07h s/f blanking control sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 08h s/f blanking monitor 0 0 0 0 vmon fvcr svcr1 svcr0 09h monitor mask 0 0 0 0 mvmon mfvcr msvcr 0 when the pdn pin goes ?l?, the registers are initialized to their default values. while the pdn pin =?h?, all registers can be accessed. do not write any data to the register over 09h.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 33 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control dem1 dem0 dif1 dif0 auto dapd mute stby r/w r/w default 0 1 1 1 1 0 1 1 stby: standby control 0 : normal operation 1 : standby mode(default). all registers are not initialized. dac : powered down and timings are reset. gain of volume#1 : fixed to 0db, source of tvout : fixed to vcrin, source of vcrout : fixed to tvin, source of monoout : fixed to vcrin, source of tvvout : fixed to vcrvin(or hi-z), source of tvrc : fixed to vcrrc(or hi-z), source of tvg : fixed to vcrg(or hi-z), source of tvb : fixed to vcrb(or hi-z), source of vcrvout : fixed to tvvin(or hi-z), source of vcrc : fixed to hi-z or vss(controlled by cio bit). mute: audio output control 0 : normal operation 1 : all audio outputs to gnd (default) dapd: dac power down control 0 : normal operation (default). 1 : dac power down. when dapd bit = ?1?, the zero-cross detection and offset calibration does not work. auto: auto startup bit 0 : auto startup disable (manual startup). 1 : auto startup enable(default). note: when the sbio1bit = ?1?(default= ?0?), the change of auto bit may cause a ?l? pulse on int pin. dif1-0: audio data interface format control 00 : 16bit lsb justified 01 : 18bit lsb justified 10 : 24bit msb justified 11 : 24bit i 2 s compatible (default) dem1-0: de-emphasis response control 00 : 44.1khz 01 : off (default) 10 : 48khz 11 : 32khz
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 34 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h switch vmute 0 vcr1 vcr0 mono vol tv1 tv0 r/w r/w default 1 0 0 1 0 1 0 1 tv1-0: tvoutl/r pins source switch 00 : dac 01 : vcrinl/r pins (default) 10 : mute 11 : (reserved) vol: monoout pin source switch 0 : bypass the volume (fixed to dac out) 1 : through the volume (default) mono: mono select for tvoutl/r pins 0 : stereo. (default) 1 : mono. (l+r)/2 vcr1-0: vcroutl/r pins source switch 00 : dac 01 : tvinl/r pins (default) 10 : mute 11 : volume #1 output vmute: mute switch for volume #1 0 : normal operation 1 : mute the volume #1 (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 r/w r/w default 0 0 0 1 1 1 1 1 l5-0: volume #1 control those registers control both lch and rch of volume #1. 111111 to 100011 : (reserved) 100010 : volume gain = +6db 100001 : volume gain = +4db 100000 : volume gain = +2db 011111 : volume gain = +0db (default) 011110 : volume gain = -2db ... 000011 : volume gain = -56db 000010 : volume gain = -58db 000001 : volume gain = -60db 000000 : volume gain = mute
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 35 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h zerocross 0 vmono cal dvol1 dvol0 zero ztm1 ztm0 r/w r/w default 0 0 1 0 0 1 1 1 ztm1-0: the time length control of zero-cross timeout 00 : typ. 256/fs 01 : 512/fs 10 : 1024/fs 11 : 2048/fs (default) zero: zero-cross detection enable for volume #1 control 0 : disable the volume value changes immediately without zero-cross. 1 : enable (default) the volume value changes when timeout or zero-cross before timeout. this function is disabled when stby bit = ?1?. dvol1-0: volume #0/volume #2 control. please refer the table 6 and table 7 cal: offset calibration enable 0 : offset calibration disable. 1 : offset calibration enable(default) vmono: mono select for vcroutl/r pins 0 : stereo. (default) 1 : mono. (l+r)/2
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 36 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h video switch vrf1 vrf0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 r/w r/w default 1 0 0 1 1 1 0 0 vtv0-2: selector for tv video output please refer the table 12. vvcr0-2: selector for vcr video output please refer the table 13 rf0-1: selector for rfv pin output (when yc bit=0). please refer the table 14. addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h output enable cio tvfb vcrc vcrv tvb tvg tvr tvv r/w r/w default 0 0 0 0 0 0 0 0 tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control (please refer the table 15) tvfb: tvfb output control 0 : hi-z (default) 1 : active. when the cio pin = ?1?, the vcrc pin is connected to gnd even if vcrc= ?0?. when the cio pin = ?0?, the vcrc pin follows the setting of vcrc bit. cio: vcrc pin i/o control please refer the table 15.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 37 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h video volume 0 vclp1 vclp0 yc clamp1 clamp0 vvol1 vvol0 r/w r/w default 0 0 0 0 0 1 0 0 vvol1-0: rgb video gain control 00: +6db (default) 01: +7.2db 10: +8.2db 11: +9.1db clamp1 : encoder r/chroma (encrc pin) input clamp control 0 : dc restore clamp active (for red signal. default) 1 : biased (for chroma signal.) clamp0 : vcr r/c (vcrc pin) input clamp control 0 : dc restore clamp active (for red signal) 1 : biased (for chroma signal. default.) yc : y/c mixing output control for rfv pin 0 : follow vrf1-0 bits (default) 1 : y/c mixing from tvvout and tvrc. vclp1-0 : dc restore source control 00: encv pin (default) 01: ency pin 10: vcrvin pin 11: (reserved) when the auto bit = ?1?, the source is fixed to vcrvin pin. addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h s/f blanking sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 r/w r/w default 0 0 0 0 0 0 0 0 fb1-0: tv fast blanking output control (for tvfb pin) 00: 0v (default) 01: 4v 10: follow vcr fb input (4v/0v) 11: (reserved) sbt1-0: tv slow blanking output control (for tvsb pin. minimum load is 10kohm.) 00: <2v (default) 01: 5v<, <7v 10: (reserved) 11: 10v< sbv1-0: vcr slow blanking output control (for vcrsb pin. minimum load is 10kohm) 00: <2v (default) 01: 5v<, <7v 10: (reserved) 11: 10v< sbio1-0: tv/vcr slow blanking i/o control (please refer the table 21)
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 38 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h sb/fb monitor 0 0 0 0 vmon fvcr svcr1 svcr0 r/w read default 0 0 0 0 0 0 0 0 svcr1-0: vcr slow blanking status monitor svcr1-0 reflect the voltage at vcrsb pin only when the vcrsb is in the input mode. when the vcrsb is in the output mode, svcr1-0 hold previous value. vcrsb pin input level svcr1 svcr0 < 2v 0 0 4.5 to 7v 0 1 (reserved) 1 0 9.5< 1 1 table 25. vcr slow blanking monitor fvcr: vcr fast blanking input level monitor this bit is enabled when tvfb bit = ?1?. vcrfb pin input level fvcr <0.4v 0 1 v< 1 table 26. vcr fast blanking monitor (typical threshold is 0.7v) vmon : video input monitor 0 : no video signal detected via tvvin pin and vcrvin pin. 1 : detects video signal via tvvin pin or vcrvin pin. addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h monitor mask 0 0 0 0 mvmon mfvcr msvcr 0 r/w r/w default 0 0 0 0 1 0 0 0 mvmon: video input monitor mask. please refer the table 24. mfvcr: fvcr monitor mask. 0 : the int pin reflects the change of mfvcr bit. (default) 1 : the int pin does not reflect the change of mfvcr bit. msvcr: svcr1-0 monitor mask. 0 : the int pin reflects the change of svcr1-0 bit. (default) 1 : the int pin does not reflect the change of svcr1-0 bit.
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 39 - system design tv scart y/cvbs r/c g b audio l audio r y/cvbs audio l audio r fast blank slow blank encoder y r/c g/cvbs b cvbs/y c vcr scart y/cvbs r/c g b audio l audio r y/cvbs audio l audio r fast blank slow blank audio mono cvbs rf mod mpeg decoder bick lrck sdata mclk micro processor sda sck pdn phono encv ency vcrvin tvvout encc encrc encgv encb sck sda pdn bick lrck sdti mclk vcrrc vcrc vcrg vcrb vcrinl vcrinr vcrvout vcroutl vcroutr vcrsb vcrfb tvfb tvoutl tvoutr tvvin tvrc tvg tvb tvinl tvinr tvsb rfv monoout interrupt int figure 18. typical connection diagram
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 40 - ? grounding and power supply decoupling vd, vp, vvd1, vvd2, vss and vvss should be supplied from analog supply unit with low impedance and be separated from system digital supply. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these pins to eliminate the effects of high frequency noise. the 0.1 f ceramic capacitor should be placed as near to vd (vp, vvd1, vvd2) as possible. ? voltage reference each dvcom/pvcom are signal ground of this chip. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these vcom pins to eliminat e the effects of high frequency noise. no load current may be drawn from these vcom pins. all signals, especially clocks, should be kept away from these vcom pins in order to avoid unwanted coupling into the AK4704. ? analog audio outputs the analog outputs are also single-ended and centered on 5.6v(typ.). the output signal range is typically 2vrms (typ@vd=5v). the internal sw itched-capacitor filter and continuous-tim e filter attenuate the noi se generated by the delta-sigma modulator beyond the audio pass band. therefore, an y external filters are not required for typical application. the output voltage is a positive full scale for 7fffffh (@24bit) and a negative full scale for 800000h (@24bit). the ideal output is 5.6v(typ.) for 000000h (@24bit). the dc voltage on analog outputs are eliminated by ac coupling. ? filt pin the c (0.1 f) should be attached as shown in the figure 19. AK4704 c=0.1uf filt vvss figure 19. filt pin
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 41 - ? external circuit example analog audio input pin monoin tvinl/r vcrinl/ r dacl/r 0.47f 300ohm (cable) analog audio output pin monoout tvoutl/r vcroutl/r 10f 300ohm total > 4.5kohm (cable) analog video input pin encv, ency, vcrvin, tvvin, encrc, encc, vcrrc, encg, vcrg, encb, vcrb 0.1f 75ohm (cable) 75ohm analog video output pin tvvout, tvrc tvg, tvr, rfv vcrvout, vcrc max 400pf 75ohm 75ohm max 15pf (cable)
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 42 - slow blanking pin tvsb vcrsb max 3nf (with 400ohm) 400ohm (max 500ohm) min: 10k ohm (cable) fast blanking input pin vcrfb 75ohm (cable) 75ohm fast blanking output pin tvfb 75ohm 75ohm (cable)
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 43 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp(unit:mm) 0.10 37 24 25 36 0.145 0.05 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.5 0.2 0.5 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei akm confidential [AK4704] rev. 0.5 2004/1 - 44 - marking AK4704vq xxxxxxx 1 xxxxxxxx: date code identifier important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulati ons of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4704

	To Download AK4704 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .